Appearance
2.4 — The MOSFET and the FET Family
Volume I, Chapter 1.1 said that applying a voltage to the gate makes a channel appear, and then admitted it was not going to explain how. This is where the channel appears properly, with the physics on the page.
The MOSFET is the most manufactured object in human history. A modern processor holds tens of billions of them, and world production runs into the sextillions. Everything about computing rests on one property: the gate is insulated, so controlling the device costs no steady current at all.
1. Field-effect versus bipolar, in one comparison
| BJT | MOSFET | |
|---|---|---|
| Controlled by | base current | gate voltage |
| Steady input current | I_C/\beta | zero |
| Carriers involved | both electrons and holes | one kind only |
| On-state loss | V_{CE(sat)} ≈ 0.2 V, fixed | I^2R_{DS(on)}, falls with better parts |
| Paralleling | needs balancing resistors | self-balancing |
| Static damage | tolerant | fragile gate |
"Bipolar" in BJT means both carrier types matter — electrons injected into a p-type base full of holes. A field-effect transistor is unipolar: only one carrier type does the conducting. That is why it has no minority carrier storage and therefore no reverse recovery delay, which is why it switches so much faster.
2. Structure of an n-channel enhancement MOSFET
Start with lightly doped p-type silicon, called the substrate or body. Diffuse two heavily doped n+ regions into the top, some distance apart: these are the source and the drain. Grow a very thin layer of silicon dioxide — glass — over the gap between them. Deposit a conductor on top of that oxide: the gate.
That is the whole device, and its name is a description of the sandwich: Metal, Oxide, Semiconductor Field Effect Transistor. Modern gates are heavily doped polysilicon or a metal again, but the name stuck from the 1960s.
The gate touches nothing electrically. It is separated from the silicon by an oxide layer a few nanometres thick — in a modern process, under ten atomic layers. It is a capacitor plate, nothing more.
3. How the channel forms — the piece Volume I deferred
With the gate at 0 V, you have n+ source, p substrate, n+ drain. That is an npn sandwich with no base drive — two diodes back to back — and whichever way you apply voltage, one of them is reverse biased. No current flows. The device is off, and off means genuinely off, with only picoamps of junction leakage.
Now apply a small positive gate voltage. The gate is one plate of a capacitor and the substrate is the other. A positive charge on the gate repels the mobile holes in the p-type silicon just under the oxide, pushing them down into the bulk. What is left behind is a thin layer containing only the fixed negative acceptor ions — a depletion region, exactly the kind Chapter 2.1 described, but created by a gate voltage rather than by a junction.
Raise the gate voltage further. The field is now strong enough to attract the minority electrons of the p-type substrate — the rare ones from the np = n_i^2 relation — up to the surface. They accumulate in that thin layer under the oxide.
At some point the electron concentration at the surface exceeds the hole concentration in the bulk. The surface layer is now, electrically, n-type material. It has been inverted. And because it is n-type and sits between two n+ regions, it connects the source to the drain.
The gate voltage at which this happens is the threshold voltage V_{th}, typically 0.4 V in logic processes and 2 to 4 V in power devices.
That is the answer Volume I promised. The channel is not built into the device; it is a layer of the substrate's own minority carriers, dragged to the surface and held there by the gate's field. Remove the gate voltage and they disperse in nanoseconds and the channel vanishes. There is nothing physical to wear out, and the gate never passes current because the oxide is a genuine insulator.
Why "enhancement" and "depletion"
An enhancement-mode device has no channel until you make one — it is off at zero gate voltage, which is what logic wants, and it is what essentially all digital MOSFETs are.
A depletion-mode device has a channel built in during manufacture and you apply a gate voltage to remove it — it is on at zero gate voltage. Rare, used in a few analog current sources and in the JFET of section 8.
4. The two operating regions and the equations
Once a channel exists, apply a drain-source voltage V_{DS} and current flows.
Triode region (also called linear or ohmic)
For small V_{DS}, the channel behaves as a resistor whose value the gate controls:
I_D = k\left[(V_{GS}-V_{th})V_{DS} - \frac{V_{DS}^2}{2}\right] \qquad\text{for } V_{DS} \lt V_{GS}-V_{th}
where k = \mu_nC_{ox}(W/L), gathering the mobility, the oxide capacitance per unit area, and the channel's width-to-length ratio.
For very small V_{DS} the squared term vanishes and this reduces to a straight line — the device is simply a resistor of value
R_{DS(on)} = \frac{1}{k(V_{GS}-V_{th})}
This is the region a MOSFET switch operates in when it is on, and R_{DS(on)} is the number on the front page of every power MOSFET datasheet. Good modern parts reach single-digit milliohms.
Saturation region
Raise V_{DS} and something counter-intuitive happens. The channel's thickness depends on the voltage between the gate and the silicon directly beneath it. Near the source that is V_{GS}. Near the drain it is V_{GS} - V_{DS}, which is smaller. So the channel is thinner at the drain end.
When V_{DS} reaches V_{GS}-V_{th}, the voltage across the oxide at the drain end has fallen exactly to threshold, and the channel closes there. That is pinch-off.
Push V_{DS} higher and the pinch point moves slightly back towards the source, but the voltage across the remaining channel stays fixed at V_{GS}-V_{th}. The extra voltage is dropped across the pinched-off gap, and carriers are simply swept across it by the field. So the current stops increasing:
\boxed{I_D = \frac{k}{2}\left(V_{GS}-V_{th}\right)^2} \qquad\text{for } V_{DS} \ge V_{GS}-V_{th}
The square law. Compare it with the BJT's exponential — the MOSFET's control curve is far gentler, which means lower gain for the same current, but also much better linearity and far less temperature sensitivity.
In saturation the device is a voltage-controlled current source, which is the analog amplifier's ideal element. Its transconductance:
g_m = \frac{dI_D}{dV_{GS}} = k(V_{GS}-V_{th}) = \sqrt{2kI_D}
Compare with the BJT's g_m = I_C/26\ \text{mV}. At 1 mA a BJT gives 38.5 mA/V; a typical small MOSFET at 1 mA might give 2 mA/V. The BJT wins on gain by roughly twenty to one at the same current — which is why precision analog circuits still use bipolar input stages, and why MOSFET amplifiers need larger resistors or more stages.
A confusing naming clash worth flagging
"Saturation" means opposite things for the two devices. A saturated BJT is fully on, with almost no voltage across it. A saturated MOSFET is in its current-source region, with substantial voltage across it — the equivalent of a BJT's active region. The MOSFET's fully-on switch state is called the triode region. This trips up everyone at least once.
5. The MOSFET as a switch
The dominant use, and the one the whole digital world rests on.
Before the numbers, the plain version. A MOSFET is a tap whose handle is a voltage rather than a hand. Nothing flows through the handle — the gate is insulated, so it draws no steady current at all — and yet the voltage you put on it decides whether the pipe from source to drain is open or shut. There are two kinds of tap, and they are opposites, which is the whole point of the pair.
Why the two types are opposites, in one paragraph, using only section 3's mechanism. An NMOS sits in a p-type body, so the carriers it has to drag to the surface are electrons, and pulling electrons upward needs a positive gate. A PMOS sits in an n-type body, so the carriers it drags up are holes, and pulling holes upward needs a negative gate — meaning a gate below the source, which in a logic circuit is a gate near ground while the source sits at the supply. Same physics, opposite doping, opposite polarity. Nothing else differs.
Off state: V_{GS} = 0, well below V_{th}. No channel, leakage in the nanoamps.
On state: V_{GS} well above V_{th}, deep in triode. The device is a resistor of R_{DS(on)}, and the loss is I^2R_{DS(on)}.
Worked example. A power MOSFET with R_{DS(on)} = 8\ \text{m}\Omega switching 20 A:
P = 20^2\times0.008 = 3.2\ \text{W}
The equivalent BJT would drop V_{CE(sat)} \approx 0.3 V at that current, giving 0.3\times20 = 6 W. The MOSFET halves the loss, and it can be improved further just by buying a bigger one — whereas a BJT's saturation voltage is set by physics and barely improves. That is why every switching supply, motor drive and battery protection circuit built since about 1990 uses MOSFETs.
Note the different scaling, though. MOSFET loss goes as I^2; BJT loss goes as I. At very high currents the BJT (or the IGBT, a hybrid device) eventually wins again, which is why traction and grid-scale converters still use IGBTs.
Gate drive — where the real design problem is
The gate draws no steady current, but it is a capacitor of typically 1 to 10 nF, and switching it means charging and discharging that capacitance fast.
Q_G = C_{GS}V_{GS}, \qquad I_{peak} = \frac{Q_G}{t_{switch}}
Worked example. Q_G = 50 nC, wanting to switch in 50 ns:
I = \frac{50\times10^{-9}}{50\times10^{-9}} = 1\ \text{A}
A whole amp, to drive a gate that draws nothing at DC. This is why gate driver chips exist and why you cannot switch a power MOSFET quickly straight from a microcontroller pin. Drive it too slowly and the device spends too long in its high-dissipation middle region, and the switching loss cooks it.
There is a further complication called the Miller plateau: during switching, the gate-drain capacitance must also be charged while the drain voltage swings, and this holds the gate voltage flat partway up for a while. Most of the switching loss happens during that plateau, and shortening it is the main job of a gate driver.
The body diode, which you cannot remove
The p substrate and the n+ drain form a PN junction, and in almost every discrete MOSFET the substrate is tied to the source internally. So there is a diode permanently across the device, from source to drain. It cannot be designed out.
Sometimes it is a gift: in a motor bridge it does the flyback job for free. Sometimes it is a hazard: it means a MOSFET can only block voltage in one direction, so to switch AC you need two MOSFETs back to back. And in fast switching applications its slow reverse recovery is a real loss mechanism, which is why some parts have a faster body diode as a selling point.
6. CMOS — closing the loop with Volume I
Chapter 1.1 of Volume I described CMOS as a switch pair. Now the pieces are all present.
A PMOS transistor is the mirror image: n-type substrate, p+ source and drain, and it turns on when the gate is pulled low. An NMOS turns on when the gate goes high.
Put one of each in series between the supply and ground, with their gates tied together as the input and their junction as the output. That is a CMOS inverter:
- Input high: NMOS on, PMOS off. Output pulled to ground. Output low.
- Input low: PMOS on, NMOS off. Output pulled to supply. Output high.
Trace the left panel with a finger. The input is at 0 V. That is below the PMOS threshold, so the PMOS conducts and the green path runs from the supply down to the output. The same 0 V is below the NMOS threshold too, so the NMOS is open and the path to ground is broken. The output can only be pulled up, so it goes high. The right panel is the same walk with every state reversed.
And now notice what the picture makes obvious that the words did not. There is no path from supply to ground in either state — one switch is always open. Whatever the input, the supply is never shorted to ground through the gate.
In either steady state, exactly one transistor is off, so no current flows from supply to ground at all. A CMOS gate holding a value consumes essentially nothing. That is the property that made large-scale integration possible, because a chip with a billion gates that each drew a milliamp would need a megawatt.
Power is consumed only when switching, charging and discharging the capacitance of the next stage:
P_{dynamic} = \alpha CV^2f
where \alpha is the fraction of gates switching each cycle, C the load capacitance, V the supply, and f the clock frequency.
Read that equation carefully, because it is the single most consequential formula in modern computing. Power scales with the square of supply voltage, which is why chip supplies fell from 5 V to 3.3 V to 1.8 V to under 1 V. It scales linearly with frequency, which is why clock speeds stopped climbing around 2005 and the industry pivoted to multiple cores instead. And the leakage term that this equation ignores is what stopped voltages falling further, because a lower supply needs a lower threshold, and a lower threshold leaks exponentially more.
7. Static electricity, and why MOSFETs come in foil
The gate oxide is a few nanometres thick. Its breakdown field is around 10^9 V/m, so a few nanometres withstands only 10 to 20 V. A static discharge from your finger can be several thousand volts.
Once the oxide punches through, it is a permanent hole. The device may still half-work, which is worse than outright failure because the fault is intermittent and hard to find.
Every modern MOSFET and every integrated circuit input therefore has protection diodes to the rails, exactly the clamp described in Chapter 2.2. They handle ordinary handling static. They do not handle carelessness, which is why parts ship in conductive foam and bags and why assembly benches are grounded.
A related trap: never leave a MOSFET gate floating. An unconnected gate is a capacitor with no discharge path, and stray coupling will drift it to any voltage at all, turning the device randomly on. Every gate needs either an active driver or a pull-down resistor, and a design that omits one behaves unpredictably in ways that look like a software bug.
8. The rest of the FET family
JFET
The junction field-effect transistor predates the MOSFET and works differently. A bar of n-type silicon carries current from source to drain; a p-type gate region surrounds it. Reverse-bias the gate and its depletion region grows into the bar, squeezing the conducting channel narrower. More reverse bias, narrower channel, less current.
Key points:
- It is depletion mode — full current at zero gate voltage, pinching off at some negative V_{GS(off)}, typically -2 to -8 V.
- The gate is a reverse-biased junction, not an insulator, so it does draw a small leakage current — picoamps, but not zero.
- It cannot be forward biased, because then the gate junction conducts and the device stops behaving like a FET.
JFETs survive because they have exceptionally low noise, which is why they still appear at the input of high-quality microphone preamplifiers, instrumentation amplifiers and electrometers. The current-source made from a JFET with its gate tied to its source is also a common one-component trick.
MESFET and HEMT
Replacing the junction gate with a metal-semiconductor Schottky contact gives a MESFET, and building the channel from a layer of gallium arsenide where electrons move far faster gives the HEMT (high electron mobility transistor). These are the devices in satellite receivers, radar and phone base stations, working comfortably into the tens of gigahertz, where silicon cannot follow. Chapter 7.6 meets them again.
IGBT
The insulated gate bipolar transistor is a genuine hybrid: a MOSFET gate driving a bipolar output structure. You get the MOSFET's easy voltage drive with the BJT's low conduction loss at very high current, at the cost of slower switching and a fixed voltage drop of about 2 V. It dominates above roughly 600 V and 50 A — electric vehicle traction inverters, industrial motor drives, induction hobs, and the grid converters in Chapter 9.5.
Wide-bandgap devices
Silicon carbide and gallium nitride have band gaps of 3.3 and 3.4 eV against silicon's 1.12 (Chapter 2.1). A wider gap means the material withstands roughly ten times the electric field before breaking down, so a device blocking the same voltage can be ten times thinner, giving far lower resistance and far less capacitance. That is why GaN phone chargers are a third the size of the old ones — higher switching frequency means smaller inductors and capacitors, and the smaller magnetics are what shrink the brick.
9. Choosing between them, honestly
| Need | Choose | Because |
|---|---|---|
| Digital logic | CMOS | zero static power |
| Switching under ~200 V | MOSFET | low R_{DS(on)}, fast |
| Switching above ~600 V, high current | IGBT | conduction loss wins |
| High-frequency, small-signal | HEMT / MESFET | carrier speed |
| Low-noise analog input | JFET or bipolar | noise floor |
| Precision analog gain | BJT | 20× the transconductance |
| Compact high-frequency power | GaN / SiC | field strength |
Both transistor families are now on the table, and both are awkward to design with directly — gain varies, bias drifts, and every circuit is a compromise. The next chapter takes dozens of them, puts them on one chip, wraps feedback around the result, and produces a building block so well behaved that you can design with it using two rules and no device physics at all.
Every formula above, built from scratch
None of the results in this chapter are worth memorising, because each one can be rebuilt in under a minute from something simpler. What follows is that rebuilding, one result at a time, so the formula and the reason for it sit on the same page as the explanation that needed them.
The MOSFET
Triode region, V_{DS} \lt V_{GS}-V_{th}:
I_D = k\left[(V_{GS}-V_{th})V_{DS}-\frac{V_{DS}^2}{2}\right], \qquad k = \mu_nC_{ox}\frac WL
For small V_{DS}:
R_{DS(on)} = \frac{1}{k(V_{GS}-V_{th})}
Saturation, V_{DS} \ge V_{GS}-V_{th}:
I_D = \frac k2(V_{GS}-V_{th})^2(1+\lambda V_{DS})
with \lambda the channel-length modulation parameter, the MOSFET's counterpart of the Early effect.
g_m = k(V_{GS}-V_{th}) = \sqrt{2kI_D} = \frac{2I_D}{V_{GS}-V_{th}}
Compare the two devices at 1 mA: BJT gives g_m = 38.5 mA/V from I_C/V_T; a small MOSFET might give 2 mA/V. The BJT's exponential beats the MOSFET's square law by roughly twenty to one.
Gate charge and switching
Q_G = C_{iss}V_{GS}, \qquad I_{drive} = \frac{Q_G}{t_{switch}}
P_{conduction} = I_D^2R_{DS(on)}, \qquad P_{switching} \approx \tfrac12 V_{DS}I_D(t_{on}+t_{off})f
CMOS
P_{dynamic} = \alpha CV^2f, \qquad P_{static} = I_{leak}V
Where the V^2 comes from: charging a capacitance C to voltage V stores \tfrac12CV^2 and dissipates the same again in the resistance of the transistor doing the charging, so a full charge-discharge cycle costs CV^2. Multiply by frequency and by the fraction of gates that switch.
What the next chapter fixes
Both the BJT and the MOSFET amplify, and both need supporting components chosen with care to do it well. Chapter 2.5 covers the part that removes most of that work: an amplifier built from dozens of transistors and sold as one component, whose behaviour depends almost entirely on two resistors you choose rather than on anything inside it.