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5.6 — Where DSP Actually Runs
Everything in Part 5 has been mathematics. This chapter is about where it executes, what it costs, and why the same algorithm is a good idea in one product and impossible in another.
This chapter costs out the algorithms of Chapters 5.1 to 5.5 in operations and in energy, using the number representations of Volume I Chapter 1.4 — because an algorithm that is correct in mathematics and too slow in silicon has not solved anything.
1. The four places DSP runs
A general-purpose processor. Flexible, easy to program, and inefficient per operation. Fine when the sample rate is low or a computer is present anyway. A modern desktop core does a few billion multiply-accumulates per second using its vector instructions.
A DSP chip. A processor whose instruction set is built around the inner loop of a filter. Three features distinguish it:
- A single-cycle multiply-accumulate with an extended-precision accumulator — typically 40 bits for 16-bit data, so thousands of products can be summed without overflow.
- Harvard architecture with multiple memory buses, so a coefficient, a sample and an instruction can all be fetched in the same cycle.
- Circular addressing, where an address register wraps automatically at a buffer boundary. This is the whole reason a delay line costs nothing — without it, every sample would need a bounds check and a branch.
Zero-overhead loops complete the picture: the hardware repeats a block a fixed number of times with no branch instruction at all.
Together these let a DSP execute one filter tap per cycle, where a general processor might take five.
An FPGA. Chapter 3.6 covered it. Genuinely parallel, so a 64-tap filter runs in one clock. Right when the data rate is beyond any processor.
Fixed-function hardware. A dedicated block on a chip, doing one job with no flexibility and the lowest possible power. Every phone has hardware blocks for video decoding, image processing and audio codecs, because doing those in software would drain the battery in an hour.
The decision, in one line: low rate and changing requirements means software; high rate and fixed requirements means hardware; and the interesting cases are in between.
2. Fixed point versus floating point
Floating point stores a mantissa and an exponent, so it covers an enormous dynamic range and you rarely think about scaling. Costs more silicon and more power.
Fixed point stores integers with an implied binary point. Cheaper and lower power, and it forces you to manage the numeric range yourself.
The notation is Q-format: Q15 means one sign bit and fifteen fractional bits, representing values from -1 to +0.99997 in a 16-bit word. Q31 is the 32-bit equivalent.
Multiplying two Q15 numbers gives Q30, so the result must be shifted left by one and the top 16 bits taken to get back to Q15. Forgetting that shift is the classic fixed-point bug, and it produces output exactly half the intended amplitude.
The dynamic range:
\text{range}=6.02n\ \text{dB}
16-bit fixed point gives 96 dB; 32-bit gives 192 dB; 32-bit float gives about 1500 dB. For audio, 24-bit fixed point is comfortable and 16-bit is tight — the accumulated round-off through a long filter chain becomes audible.
Where each is used. Battery-powered and high-volume products use fixed point, because the power and die area matter. Anything with a general processor uses floating point, because it is free there and eliminates a whole class of bug. Most modern DSP chips include floating-point hardware, so the argument has largely been settled by silicon getting cheaper.
3. The block diagram every DSP product shares
The point of drawing it: every product below is this chain with different boxes. And the most common engineering mistake is to optimise the processor while the anti-alias filter is missing or the analog front end is noisy.
4. Your phone
Perhaps a dozen distinct DSP systems, running simultaneously.
The modem is the largest. Chapter 8.1 covers it properly, but the DSP content is enormous: channel estimation, equalisation, turbo decoding, and the OFDM transform of Chapter 7.4 — which is an FFT, running thousands of times per second.
The camera image pipeline. Demosaicing (reconstructing full colour from the Bayer filter's one-colour-per-pixel sensor), noise reduction, lens distortion correction, high dynamic range merging of several exposures, and the JPEG or HEIC encoder of Chapter 5.5. This runs in fixed-function hardware, because doing it in software would take seconds per photograph and drain the battery.
Audio. Echo cancellation so the far end does not hear themselves, beamforming from two or three microphones to favour your voice over the room, noise suppression, and the codec.
Always-on wake word detection. A tiny neural network running continuously on a dedicated low-power core, drawing under a milliwatt, listening for one phrase. It cannot run on the main processor — that would cost tens of milliwatts and halve the standby time.
Sensor fusion. Accelerometer, gyroscope and magnetometer combined by a Kalman filter to estimate orientation. Volume II, Chapter 7.7 covers the estimation theory; the point here is that three noisy sensors with complementary weaknesses produce one good estimate.
5. Your car
Engine control samples crankshaft position, air flow and oxygen content, and computes ignition timing and fuel injection duration hundreds of times per second — with hard real-time deadlines, since being late by a millisecond means firing at the wrong crank angle.
Anti-lock braking measures each wheel's speed, detects the onset of lock by watching deceleration rate, and modulates brake pressure at about 15 Hz. The characteristic pulsing you feel through the pedal is the control loop running.
Radar. 77 GHz automotive radar transmits a frequency-swept chirp and measures the beat frequency of the return, which gives range and, via the Doppler shift, closing speed. The processing is an FFT in two dimensions — one across the chirp for range, one across successive chirps for velocity — producing a range-Doppler map. Chapter 7.1 covers the radio side.
Active noise cancellation in the cabin, using the same principle as Chapter 5.4 with microphones in the headliner and the car's own speakers, targeting engine and road rumble below about 300 Hz.
6. A hospital
ECG. The heart's signal is about 1 mV, sitting on top of interference from the mains that can be tens of millivolts. The chain is: an instrumentation amplifier for common-mode rejection (Chapter 2.5), a high-pass filter at 0.5 Hz to remove baseline drift from breathing, a notch at 50 or 60 Hz for the mains (Chapter 4.6 built exactly this), and a low-pass at 100 Hz. Then QRS complex detection — usually the Pan-Tompkins algorithm, which is bandpass filtering, differentiation, squaring and moving-window integration, all techniques from this Part.
Ultrasound. A phased array of transducers, with the transmit timing of each element adjusted so the wavefronts add constructively in a chosen direction — beamforming, which is the spatial equivalent of a filter. The received echoes are processed the same way to focus at each depth. The image is built from time-of-flight, and the Doppler shift of moving blood gives the colour overlay.
MRI. The received signal is literally sampled in the spatial frequency domain — physicists call it k-space — and the image is produced by a two-dimensional inverse FFT. This is the most direct use of Chapter 5.1 anywhere in medicine, and it is why MRI became practical only after the FFT existed. Compressed sensing (Chapter 4.7) now allows fewer measurements and shorter scans.
Pulse oximetry. Two LEDs, red and infrared, shone through a fingertip, with a photodiode measuring transmitted light. Oxygenated and deoxygenated haemoglobin absorb the two wavelengths differently, so the ratio of the pulsating components at the two wavelengths gives oxygen saturation. The DSP job is extracting a small pulsating component from a large steady one in the presence of motion — which is a filtering and adaptive-cancellation problem.
7. Your headphones
Covered in Chapter 5.4, and worth restating as a system: microphones, an adaptive filter, a codec if wireless, and a DAC with its reconstruction filter — the whole of Part 5 in an object that fits in an ear and runs for eight hours on a battery smaller than a coin.
The power budget is what shapes the design. A 60 mAh battery at 3.7 V holds 800 joules. Over eight hours that is 27 mW total, of which the radio takes perhaps 10 mW and the amplifier 8 mW, leaving under 10 mW for all the processing. That constraint is why the noise cancelling runs on a fixed-function block rather than a general processor, and why the codec is chosen as much for its decoding cost as for its quality.
8. What limits real designs
Four constraints, in the order they usually bite.
Computation. Count the multiply-accumulates per second and compare with what the hardware delivers, remembering that real code achieves perhaps 50 to 70% of the peak figure.
Worked example. 8 channels at 48 kHz through 64-tap FIR filters:
8\times48{,}000\times64=24.6\ \text{million MACs/s}
A 100 MHz DSP doing one per cycle handles it at 25% load — comfortable. Now make it 512 taps and it is 197 million, which exceeds the chip entirely.
Memory. A 512-tap filter needs 512 coefficients plus a 512-sample delay line per channel. In 32-bit words for 8 channels that is 8\times512\times4\times2 = 32 KB, which exceeds many microcontrollers' entire RAM.
Latency. Total delay is the input buffer plus the algorithm plus the output buffer. The acceptable figure varies enormously by application, and this is what usually decides the architecture:
| Application | Budget |
|---|---|
| Live musician monitoring | under 5 ms |
| Voice call | under 150 ms round trip |
| Hearing aid | under 10 ms |
| Video playback | one frame, 33 ms |
| Offline processing | unlimited |
The hearing aid number is the demanding one. Above about 10 ms the wearer hears their own voice conducted through the skull and again through the aid, slightly delayed, which is deeply unpleasant. That single constraint rules out long FIR filters and FFT-based processing, and it is why hearing aids use short IIR filter banks rather than the FFT approach that would otherwise be natural.
Power. P = CV^2f from Chapter 2.4 still governs. Halving the clock halves the power; halving the supply quarters it. The standard strategy is to run as slowly as the deadline allows and sleep the rest of the time, which is why DSP code is often written to process in blocks rather than sample by sample — one burst of activity followed by a long sleep beats continuous low-level activity.
9. Where to be careful
Five failures that recur across every application.
No anti-alias filter. The most common and the most fatal, because the damage is done before your code runs. Check it exists before debugging anything else.
Fixed-point overflow. Works in the lab with quiet signals, produces bursts of noise on a loud input. Test with full-scale signals, always.
IIR limit cycles. A stable filter oscillating quietly on zero input, from Chapter 5.2. Add dither or use floating point.
Assuming the FFT gives resolution. Zero-padding does not separate two nearby tones (Chapter 5.1). Only a longer record does.
Optimising the algorithm while the analog front end is the limit. A 24-bit converter fed from a noisy amplifier gives you 14 real bits, and no amount of processing recovers the rest. Measure the noise floor of the analog chain before choosing the converter, not after.
Part 6 turns to systems that do not merely process a signal but act on the world and measure the result — where the feedback that Chapter 2.6 used to make an oscillator is instead used to make something behave.
Every formula above, built from scratch
None of the results in this chapter are worth memorising, because each one can be rebuilt in under a minute from something simpler. What follows is that rebuilding, one result at a time, so the formula and the reason for it sit on the same page as the explanation that needed them.
Fixed point
\text{Q}m\text{.}n: \quad \text{value}=\frac{\text{integer}}{2^n}, \qquad \text{range}=\pm2^m
Q15 in 16 bits: range -1 to +0.99997, resolution 3.05\times10^{-5}.
Multiplication: Q15 × Q15 = Q30, so shift left by 1 and take the upper 16 bits to return to Q15.
\text{dynamic range}=6.02n\ \text{dB}
Round-off noise in a filter: each multiplication injects noise of variance q^2/12 where q is the quantisation step (the same \sqrt{12} as Chapter 3.5). In an IIR filter this noise circulates and is amplified by the filter's own gain, so it is worst at resonances.
Compute budgets
\text{MACs/s}=\text{channels}\times f_s\times\text{taps}
\text{memory}=\text{channels}\times(\text{taps}+\text{delay line})\times\text{bytes per word}
\text{latency}=t_{buffer,in}+t_{algorithm}+t_{buffer,out}
P=CV^2f
Halving the clock halves the power; halving the supply quarters it. Run slowly and sleep.
Fourteen worked problems next.
What the next chapter fixes
Parts 4 and 5 analyse signals that arrive and describe what a system does to them. Neither can make a system behave. Part 6 closes the loop: measure the output, compare it with what you wanted, and feed the difference back in — an idea simple enough to state in one line and dangerous enough that it can make a stable machine tear itself apart.